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benchdnn-2.2.4-bp154.1.58 RPM for aarch64

From OpenSuSE Leap 15.4 for aarch64

Name: benchdnn Distribution: SUSE Linux Enterprise 15 SP4
Version: 2.2.4 Vendor: openSUSE
Release: bp154.1.58 Build date: Thu May 12 06:09:35 2022
Group: Unspecified Build host: obs-arm-8
Size: 5671570 Source RPM: onednn-2.2.4-bp154.1.58.src.rpm
Packager: https://bugs.opensuse.org
Url: https://01.org/onednn
Summary: Header files of Intel Math Kernel Library
Intel Math Kernel Library for Deep Neural Networks (Intel MKL-DNN) is an
open-source performance library for deep-learning applications. The library
accelerates deep-learning applications and frameworks on Intel architecture.
Intel MKL-DNN contains vectorized and threaded building blocks that you can use
to implement deep neural networks (DNN) with C and C++ interfaces.

This package only includes the benchmark utility including its input files.

Provides

Requires

License

Apache-2.0

Changelog

* Thu Dec 02 2021 Max Lin <mlin@suse.com>
  - Skip RPATH entirely on Leap 15.4
* Tue Jun 15 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Fix build on aarch64:
    * onednn-xbyak-aarch64.patch
* Tue Jun 15 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to version 2.2.4:
    * Fixed build error with GCC 11 (eda1add)
    * Fixed an issue with reorder reporting unimplemented when
      quantizing f32 weights to s8 (4f05b76, 5d3d1e1, cc77eef)
    * Updated name for GPU gen12 architecture to xe (3d202c2)
  - Drop upstream patch:
    * 0001-common-gpu-include-thread-and-limit-headers-to-fix-G.patch
* Thu Jun 03 2021 Ferdinand Thiessen <rpm@fthiessen.de>
  - Update to version 2.2.3
    * Fixed a bug in int8 depthwise convolution ptimitive with groups
      and 1d spatial size for processors with AVX-512 and AVX2 support
    * Fixed correctness issue for PReLU primitive
    * Fixed corretness issue in reorder for blocked layouts with
      zero padding
    * Improved performance of weights reorders used by BRGEMM-based
      convolution primitive for processors with AVX-512 support
    * Added -fp-model=precise build flag for DPC++ code
    * Fixed potential memory leak in matmul primitive
    * Fixed performance of matmul primitive when fused with bias
      update and sum
    * Fixed a bug in matmul primitive when writing to non-contiguous
      destination buffer
  - Add upstream patch for GCC11 support
    * 0001-common-gpu-include-thread-and-limit-headers-to-fix-G.patch
* Thu May 27 2021 Jan Engelhardt <jengelh@inai.de>
  - Update descriptions.
* Wed May 26 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.2.2, changes:
    * Fixed performance regression in fp32 forward inner product for
    shapes with number of output channels equal to 1 for processors
    with Intel AVX-512 support (714b1fd)
    * Fixed performance regression in forward convolutions with groups
    for processors with Intel AVX-512 support(3555d4a)
    * Removed -std=c++11 build flag for DPC++ headers (1fcb867)
    * Fixed buffer access in initializing workspace in RNN
    implementation on GPU (9b03091)
    * Fixed fix a bug in convolution with 1x1 kernel and mixed
    strides on processors with Intel AVX-512 support (d0b3e3f)
    * Used getauxval for Linux to get CPU features on for AArch64
    systems (25c4cea)
    * Added -fp-model=precise build flag for DPC++ code (3e40e5e)
    * Fixed out-of-bounds writes in elementwise primitive on
    Intel Processor Graphics (bcf823c)
  - Fix build with Arm Compute Library:
    * onednn-1045.patch
* Tue Apr 13 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.2.1, changes:
    * From 2.2:
    Fixed segfault for cases when primitive descriptor or attributed contain NaN (e6d05ec, dbca1e9, 0326b09, 0326b09)
    Fixed engine creation failure for GPU subdevices (4c3a114)
    Fixed long lines clipping in verbose output (70d70a8)
    Fixed segfault in bfloat16 convolution weight gradient implementation on processors with Intel AMX support (a3a73a3)
    Fixed performance regression in binary primitive with per_oc broadcast strategy (9ac85d8)
    Worked around a bug with Microsoft Visual C++ compiler version detection in CMake 3.19 (2f39155)
    Removed -std=c++11 build flag for DPC++ code to align with SYCL standard (1b026f5)
    * Changes between 2.1 and 2.2:
    Performance Optimizations
      Intel Architecture processors
      Improved performance of int8 compute functionality for future Intel Xeon Scalable processor (code name Sapphire Rapids). The functionality is disabled by default and should be enabled via CPU dispatcher control.
      Improved performance of compute functionality for future Intel Core processor with Intel AVX2 and Intel DL Boost instructions support (code name Alder Lake).
      Improved fp32 inner product forward propagation performance for processors with Intel AVX-512 support.
      Improved dnnl_gemm performance for cases with n=1 on all supported processors.
      Intel Graphics products
      Introduced NHWC format support for activations for int8 primitives.
      AArch64-based processors
      Improved performance of fp32 and int8 convolution, and softmax primitives for processors with SVE 512 support.
      Improved performance of fp32 convolution via Arm Compute Library (ACL).
      Improved performance of convolution with a combination of sum and relu post-ops via ACL.
    Functionality
      Extended eltwise primitive with support for mish and hardswish algorithms.
      Extended binary primitive with support for comparison operators.
      Introduced support for post-ops in GPU resampling implementation.
      Introduced asymmetric quantization support for int8 deconvolution.
      Introduced binary post-ops support for matmul primitive.
    Usability
      Improved presentation of oneDNN primitives in VTune Amplifier.
      Introduced Linux perf support for AArch64.
      Introduced support for Fujitsu C++ compiler.
      Introduced a build time check for minimal supported ACL version. Currently oneDNN requires ACL 21.02 or later.
      Added support for cuDNN 8.x
* Wed Feb 17 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.1
  - Add Arm ComputeLibrary support on aarch64
* Mon Oct 05 2020 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Obsoletes mkl-dnn* <= %{version}
* Fri Oct 02 2020 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Rename mkl-dnn to onednn to follow upstream
* Wed Sep 23 2020 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 1.6.3
  - Drop upstream patch:
    * cmake-no-install-ocl-cmake.patch
* Wed Sep 23 2020 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Build on aarch64 and ppc64le which are now also supported
  - Provide oneDNN and oneDNN-devel as it is the new official name
* Tue May 05 2020 Tomáš Chvátal <tchvatal@suse.com>
  - Update to 1.4:
    * Performance improvements all over the board
  - Rebase patch cmake-no-install-ocl-cmake.patch
* Tue Mar 24 2020 Tomáš Chvátal <tchvatal@suse.com>
  - Add constraints to not crash during testing on OOM
* Thu Feb 27 2020 Tomáš Chvátal <tchvatal@suse.com>
  - Do not disable LTO there is no actual reason for that
  - Export LD_LIBRARY_PATH to fix older releases build
* Wed Feb 26 2020 Tomáš Chvátal <tchvatal@suse.com>
  - There is no actual reason to not use github tag for tarball
    fetching -> remove the service
  - Format with spec-cleaner
  - Use proper %cmake macros everywhere
  - Add configure options for cmake to set it up in a way we really
    want
  - Add patch from Debian to not install OpenCL cmake finder:
    * cmake-no-install-ocl-cmake.patch
* Thu Feb 20 2020 Christian Goll <cgoll@suse.com>
  - enabled tests
* Thu Jan 30 2020 Christian Goll <cgoll@suse.com>
  - packaged separate benchnn packae with its input files
  - updated to v1.1.3 which includes
    * Fixed the mean and variance memory descriptors in layer
    normalization (65f1908)
    * Fixed the layer normalization formula (c176ceb)
* Wed Jan 08 2020 Christian Goll <cgoll@suse.com>
  - updated to v1.1.2
    * Fixed threading over the spatial in bfloat16 batched
      normalization (017b6c9)
    * Fixed read past end-of-buffer error for int8 convolution (7d6f45e)
    * Fixed condition for dispatching optimized channel blocking in
      fp32 backward convolution on Intel Xeon Phi(TM) processor (846eba1)
    * Fixed fp32 backward convolution for shapes with spatial strides
      over the depth dimension (002e3ab)
    * Fixed softmax with zero sizes on GPU (936bff4)
    * Fixed int8 deconvolution with dilation when ih <= dh (3e3bacb)
    * Enabled back fp32 -> u8 reorder for RNN (a2c2507)
    * Fixed segmentation fault in bfloat16 backward convolution from
      kd_padding=0 computation (52d476c)
    * Fixed segmentation fault in bfloat16 forward convolution due
      to push/pop imbalance (4f6e3d5)
    * Fixed library version for OS X build (0d85005)
    * Fixed padding by channels in concat (a265c7d)
    * Added full text of third party licenses and
      copyright notices to LICENSE file (79f204c)
    * Added separate README for binary packages (28f4c96)
    * Fixed computing per-oc mask in RNN (ff3ffab)
    * Added workaround for number of cores calculation in Xbyak (301b088)
* Mon Feb 11 2019 cgoll@suse.com
  - added ARCH_OPT_FLAGS=""
* Tue Feb 05 2019 Christian Goll <cgoll@suse.com>
  - Initial checking of the Intel(R) Math Kernel Library for
    Deep Neural Networks which can be used by:
    * tensorflow
    * Caffee
    * PyTorch
    and other machine learning tools

Files

/usr/bin/benchdnn
/usr/share/benchdnn
/usr/share/benchdnn/inputs
/usr/share/benchdnn/inputs/binary
/usr/share/benchdnn/inputs/binary/harness_binary_bf16
/usr/share/benchdnn/inputs/binary/harness_binary_different_dt
/usr/share/benchdnn/inputs/binary/harness_binary_f32
/usr/share/benchdnn/inputs/binary/harness_binary_i8
/usr/share/benchdnn/inputs/binary/option_set_all
/usr/share/benchdnn/inputs/binary/option_set_minimal
/usr/share/benchdnn/inputs/binary/perf_binary_gpu
/usr/share/benchdnn/inputs/binary/shapes_ci
/usr/share/benchdnn/inputs/binary/shapes_perf_1st_conv
/usr/share/benchdnn/inputs/binary/shapes_perf_scaleshift
/usr/share/benchdnn/inputs/binary/shapes_src0_bcast
/usr/share/benchdnn/inputs/binary/test_binary_all
/usr/share/benchdnn/inputs/binary/test_binary_bfloat16
/usr/share/benchdnn/inputs/binary/test_binary_ci
/usr/share/benchdnn/inputs/binary/test_binary_different_dt_ci
/usr/share/benchdnn/inputs/binary/test_binary_gpu
/usr/share/benchdnn/inputs/bnorm
/usr/share/benchdnn/inputs/bnorm/perf_bnorm_gpu
/usr/share/benchdnn/inputs/bnorm/set_nd
/usr/share/benchdnn/inputs/bnorm/set_topologies
/usr/share/benchdnn/inputs/bnorm/set_topologies_gpu
/usr/share/benchdnn/inputs/bnorm/shapes_1d
/usr/share/benchdnn/inputs/bnorm/shapes_2d
/usr/share/benchdnn/inputs/bnorm/shapes_3d
/usr/share/benchdnn/inputs/bnorm/shapes_ci
/usr/share/benchdnn/inputs/bnorm/shapes_densenet_121
/usr/share/benchdnn/inputs/bnorm/shapes_googlenet_v2
/usr/share/benchdnn/inputs/bnorm/shapes_googlenet_v3
/usr/share/benchdnn/inputs/bnorm/shapes_large
/usr/share/benchdnn/inputs/bnorm/shapes_regressions
/usr/share/benchdnn/inputs/bnorm/shapes_resnet_50
/usr/share/benchdnn/inputs/bnorm/shapes_topologies_small
/usr/share/benchdnn/inputs/bnorm/test_bnorm_all_blocked
/usr/share/benchdnn/inputs/bnorm/test_bnorm_all_plain
/usr/share/benchdnn/inputs/bnorm/test_bnorm_bfloat16_blocked
/usr/share/benchdnn/inputs/bnorm/test_bnorm_bfloat16_plain
/usr/share/benchdnn/inputs/bnorm/test_bnorm_ci
/usr/share/benchdnn/inputs/bnorm/test_bnorm_gpu
/usr/share/benchdnn/inputs/bnorm/test_bnorm_regressions
/usr/share/benchdnn/inputs/bnorm/test_bnorm_regressions_large
/usr/share/benchdnn/inputs/concat
/usr/share/benchdnn/inputs/concat/test_concat_all
/usr/share/benchdnn/inputs/concat/test_concat_bfloat16
/usr/share/benchdnn/inputs/concat/test_concat_ci
/usr/share/benchdnn/inputs/concat/test_concat_gpu
/usr/share/benchdnn/inputs/conv
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_gpu
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_int8
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_int8_asymmetric
/usr/share/benchdnn/inputs/conv/harness_conv_auto
/usr/share/benchdnn/inputs/conv/harness_conv_deepbench
/usr/share/benchdnn/inputs/conv/harness_conv_depthwise_int8
/usr/share/benchdnn/inputs/conv/harness_conv_dilated_int8
/usr/share/benchdnn/inputs/conv/harness_conv_dw_bfloat16
/usr/share/benchdnn/inputs/conv/harness_conv_dw_bfloat16_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_f32
/usr/share/benchdnn/inputs/conv/harness_conv_f32_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_fused_depthwise
/usr/share/benchdnn/inputs/conv/harness_conv_int8
/usr/share/benchdnn/inputs/conv/harness_conv_regression_general
/usr/share/benchdnn/inputs/conv/harness_conv_saturation_int8
/usr/share/benchdnn/inputs/conv/harness_conv_tags
/usr/share/benchdnn/inputs/conv/perf_conv_bdw_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_clx_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_gen9
/usr/share/benchdnn/inputs/conv/perf_conv_skx_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_xe_lp
/usr/share/benchdnn/inputs/conv/set_all_topologies
/usr/share/benchdnn/inputs/conv/set_conv_3d
/usr/share/benchdnn/inputs/conv/set_conv_all
/usr/share/benchdnn/inputs/conv/set_conv_dw
/usr/share/benchdnn/inputs/conv/set_dilated-conv
/usr/share/benchdnn/inputs/conv/set_dilated-conv_1st
/usr/share/benchdnn/inputs/conv/set_dilated-conv_3d
/usr/share/benchdnn/inputs/conv/set_fastrcnn
/usr/share/benchdnn/inputs/conv/set_gpu
/usr/share/benchdnn/inputs/conv/set_maskrcnn
/usr/share/benchdnn/inputs/conv/set_perf_cpu_all_mb
/usr/share/benchdnn/inputs/conv/set_perf_cpu_inference_only
/usr/share/benchdnn/inputs/conv/set_perf_cpu_large_mb
/usr/share/benchdnn/inputs/conv/set_perf_cpu_small_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_all_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_large_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_small_mb
/usr/share/benchdnn/inputs/conv/set_topologies_inference_only
/usr/share/benchdnn/inputs/conv/shapes_1d
/usr/share/benchdnn/inputs/conv/shapes_1d_wavenet
/usr/share/benchdnn/inputs/conv/shapes_1x1
/usr/share/benchdnn/inputs/conv/shapes_3d
/usr/share/benchdnn/inputs/conv/shapes_3d_1st_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_2d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_gpu
/usr/share/benchdnn/inputs/conv/shapes_3d_i3d
/usr/share/benchdnn/inputs/conv/shapes_3d_resnext101
/usr/share/benchdnn/inputs/conv/shapes_3d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_unet
/usr/share/benchdnn/inputs/conv/shapes_3d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_a3c
/usr/share/benchdnn/inputs/conv/shapes_alexnet
/usr/share/benchdnn/inputs/conv/shapes_auto
/usr/share/benchdnn/inputs/conv/shapes_basic
/usr/share/benchdnn/inputs/conv/shapes_basic_gpu
/usr/share/benchdnn/inputs/conv/shapes_cosmictagger
/usr/share/benchdnn/inputs/conv/shapes_deepbench_inference_device
/usr/share/benchdnn/inputs/conv/shapes_deepbench_inference_server
/usr/share/benchdnn/inputs/conv/shapes_deepbench_training
/usr/share/benchdnn/inputs/conv/shapes_densnet
/usr/share/benchdnn/inputs/conv/shapes_dilated
/usr/share/benchdnn/inputs/conv/shapes_dilated_1d_1st_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_1d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_1d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_1d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_1d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_2d_1st_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_2d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_2d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_2d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_2d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_3d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_3d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_3d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_3d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_dilated_rfcn
/usr/share/benchdnn/inputs/conv/shapes_dw_1d_stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dw_1d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dw_1d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_dw_2d_1d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dw_2d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dw_2d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_dw_2d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_dw_2d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_dw_minibatch_2d-spatial
/usr/share/benchdnn/inputs/conv/shapes_dw_minibatch_channel_2d-spatial
/usr/share/benchdnn/inputs/conv/shapes_efficientdet
/usr/share/benchdnn/inputs/conv/shapes_fastrcnn_p1
/usr/share/benchdnn/inputs/conv/shapes_fastrcnn_p2
/usr/share/benchdnn/inputs/conv/shapes_fastrcnn_p3
/usr/share/benchdnn/inputs/conv/shapes_ffn
/usr/share/benchdnn/inputs/conv/shapes_fused_large_src
/usr/share/benchdnn/inputs/conv/shapes_fused_mobilenet_stride_1
/usr/share/benchdnn/inputs/conv/shapes_fused_mobilenet_stride_2
/usr/share/benchdnn/inputs/conv/shapes_gemm
/usr/share/benchdnn/inputs/conv/shapes_googlenet_v1
/usr/share/benchdnn/inputs/conv/shapes_googlenet_v2
/usr/share/benchdnn/inputs/conv/shapes_googlenet_v3
/usr/share/benchdnn/inputs/conv/shapes_large_padding
/usr/share/benchdnn/inputs/conv/shapes_maskrcnn_p1
/usr/share/benchdnn/inputs/conv/shapes_maskrcnn_p2
/usr/share/benchdnn/inputs/conv/shapes_mobilenet
/usr/share/benchdnn/inputs/conv/shapes_mobilenet_dw
/usr/share/benchdnn/inputs/conv/shapes_pointnet
/usr/share/benchdnn/inputs/conv/shapes_regression_1x1
/usr/share/benchdnn/inputs/conv/shapes_regression_dw
/usr/share/benchdnn/inputs/conv/shapes_regression_gemm
/usr/share/benchdnn/inputs/conv/shapes_regression_padding
/usr/share/benchdnn/inputs/conv/shapes_regression_small_spatial
/usr/share/benchdnn/inputs/conv/shapes_resnet_50
/usr/share/benchdnn/inputs/conv/shapes_resnet_50_sparse
/usr/share/benchdnn/inputs/conv/shapes_resnet_50_v1_5
/usr/share/benchdnn/inputs/conv/shapes_segnet
/usr/share/benchdnn/inputs/conv/shapes_src-transpose_padding
/usr/share/benchdnn/inputs/conv/shapes_ssd_300_voc0712
/usr/share/benchdnn/inputs/conv/shapes_ssd_mobilenet
/usr/share/benchdnn/inputs/conv/shapes_ssd_resnet34_inference
/usr/share/benchdnn/inputs/conv/shapes_ssd_resnet34_training
/usr/share/benchdnn/inputs/conv/shapes_tails
/usr/share/benchdnn/inputs/conv/shapes_tails_gpu
/usr/share/benchdnn/inputs/conv/shapes_unet
/usr/share/benchdnn/inputs/conv/shapes_vgg_11
/usr/share/benchdnn/inputs/conv/shapes_vgg_19
/usr/share/benchdnn/inputs/conv/shapes_xception
/usr/share/benchdnn/inputs/conv/shapes_yolov2
/usr/share/benchdnn/inputs/conv/test_conv_3d
/usr/share/benchdnn/inputs/conv/test_conv_3d_f32_nxc
/usr/share/benchdnn/inputs/conv/test_conv_all
/usr/share/benchdnn/inputs/conv/test_conv_all_topologies
/usr/share/benchdnn/inputs/conv/test_conv_all_topologies_f32_nxc
/usr/share/benchdnn/inputs/conv/test_conv_attrs
/usr/share/benchdnn/inputs/conv/test_conv_attrs_f32_nxc
/usr/share/benchdnn/inputs/conv/test_conv_bfloat16
/usr/share/benchdnn/inputs/conv/test_conv_bfloat16_nxc
/usr/share/benchdnn/inputs/conv/test_conv_bfloat16_ymm
/usr/share/benchdnn/inputs/conv/test_conv_ci
/usr/share/benchdnn/inputs/conv/test_conv_depthwise
/usr/share/benchdnn/inputs/conv/test_conv_dilated
/usr/share/benchdnn/inputs/conv/test_conv_dilated_f32_nxc
/usr/share/benchdnn/inputs/conv/test_conv_dt
/usr/share/benchdnn/inputs/conv/test_conv_dt_nxc
/usr/share/benchdnn/inputs/conv/test_conv_function
/usr/share/benchdnn/inputs/conv/test_conv_gemm_bfloat16
/usr/share/benchdnn/inputs/conv/test_conv_gemm_bfloat16_nxc
/usr/share/benchdnn/inputs/conv/test_conv_gemm_dt
/usr/share/benchdnn/inputs/conv/test_conv_gemm_dt_nxc
/usr/share/benchdnn/inputs/conv/test_conv_gemm_int8
/usr/share/benchdnn/inputs/conv/test_conv_gpu
/usr/share/benchdnn/inputs/conv/test_conv_gpu_ci
/usr/share/benchdnn/inputs/conv/test_conv_int8
/usr/share/benchdnn/inputs/conv/test_conv_regression
/usr/share/benchdnn/inputs/conv/test_conv_wino_f32
/usr/share/benchdnn/inputs/conv/test_conv_wino_gpu
/usr/share/benchdnn/inputs/conv/test_conv_wino_int8
/usr/share/benchdnn/inputs/deconv
/usr/share/benchdnn/inputs/deconv/harness_deconv_attrs_int8
/usr/share/benchdnn/inputs/deconv/harness_deconv_attrs_int8_asymmetric
/usr/share/benchdnn/inputs/deconv/harness_deconv_regression_general_f32
/usr/share/benchdnn/inputs/deconv/harness_deconv_regression_general_int8
/usr/share/benchdnn/inputs/deconv/set_all
/usr/share/benchdnn/inputs/deconv/shapes_1d
/usr/share/benchdnn/inputs/deconv/shapes_1x1
/usr/share/benchdnn/inputs/deconv/shapes_2d
/usr/share/benchdnn/inputs/deconv/shapes_3d
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Fabrice Bellet, Sat Mar 9 17:10:10 2024